In recent years the complexity of electronic products—smartphones, tablets, automotive vehicles, IoT, etc., is growing while the demands on overall miniaturization of these systems remain. The thickness and dimensions of semiconductor chips are reduced from generation to generation while the content of the electronic functions is expected to grow. Semiconductor manufacturing uses different techniques to answer this demand: 2.5-D, 3DIC, “Advanced Packaging”, Fanout wafer and substrate level packaging, integrating multiple electronic functions on one single silicon chip by methods such as System on Chip (SOC), new and efficient “Heterogeneous Integration” techniques, etc. One chip may integrate in one module a single to several advanced digital chips with various functions such as Digital RF, Analog, Power, Memory, Image Sensors and Microelectronic Mechanical Systems (MEMS).
Multichip modules incorporate different semiconductor chips from different processes that have no process correlation between them. Thus the deviation of performance of one chip embedded in the process, does not provide information on the process deviation of another chip.
A single low cost faulty chip can cause the failure of an expensive packaging module or of the final product. This vulnerability to failure is further aggravated by the fact that very few process steps in the advanced packaging module may be undone. Thus a faulty chip may not be removed after it has been embedded in an advanced packaging module.
Thus each die embedded in an advanced module needs to be tested and the advanced packaged module need to be tested as well, for visible external and internal defects (to rule out the existence of internal cracks that are usually formed during the die singulation process). Furthermore, discovering all hidden defects, is also important as a reliability measure. An undetected hidden defect, such as an internal crack or missing or defective internal bumps integrated between different layers, is in many cases NOT detectable by electrical test before product shipment. A hidden crack, may later, when the product is in the customers “hands”, develop into an product failure. Such field failures are most financially damaging and therefore great efforts need to be taken to prevent them before shipment.
In the prior art systems in order to inspect, detect and measure inner layers defects in the substrate such as semiconductor wafers, expensive, time—consuming or destructive methods are used, such as X-Ray light imaging, IR or UV light imaging, SEM sampling of wafers cross-sections. In regular AOI techniques known in prior art, the inside layers' defects (such as side wall cracks) are invisible—resulting in significant losses to the end users.
Thus a high throughput and efficient AOI system and method are required to prevent field failures as described above. Such a high throughput detection system and method may also be required in other technologies not limited to “Heterogeneous Integration”.